Units to do

August 28

Introduction to course and tools
Lecture (1) and Lecture (2)

Getting started with Mentor Tools - design of ALU (unit 1)
Block Diagram editor (1a)
Embedded Blocks (1b)

September 4

Simulating the design
Flow chart editor
Using pre-made components
Truth table editor

Introduction to ModelSim (1b)
Flowchart view - designing a shifter (1c)
Designing an Arithmetic subblock (1d)
Truth Table views - a comparator (1e)

September 18

VHDL architecture view
Test benches Lecture slides
Synthesis Lecture slides

Putting together the ALU (1f)
Testing the ALU (1g)
Synthesizing the ALU (unit 2)




October 2

MIPS ISA and datapath control
Lecture slides

The spim simulator (unit 3)
Project 1 - multicycle CPU design (unit 4)
Documented implementation due on October 23.

October 23

Exceptions and interrupts
Lecture slides

Handling exceptions (Units 4a)

October 30

Memory model and design synthesis
Lecture slides

Implementing the memory interface (Units 5)
Demonstration due on November 8.




November 13

Project 2:
Pipelined CPU
and cache implemetation

Two groups will work on each project.
One group will implement The CPU
and a test benchmark for The Cache.
The other group will implement the Cache
and a test benchmark for the CPU.
By the end of the term, you will have to
test  the design.  Synthesis is NOT required.

November 20


"Interface Specification" due in class

December 6


Final exams (during class)

December 13


Project 2 due

Final project checkoff procedure

Acknowledgment: The material used in this course has been prepared and compiled by Professor Don Chiarulli.
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