Week(s) |
Topics |
Units to do |
August 28 |
Introduction to course and tools |
Getting
started with Mentor Tools - design of ALU (unit 1) |
September 4 |
Simulating the design |
Introduction
to ModelSim (1b) |
September 18 |
VHDL architecture view |
Putting
together the ALU (1f) |
. |
. |
. |
October 2 |
MIPS ISA and datapath control |
The spim
simulator (unit 3) |
October 23 |
Exceptions and interrupts |
|
October 30 |
Memory model and design synthesis |
Implementing the memory
interface (Units 5) |
. |
. |
. |
November 13 |
Project 2: |
Two groups will work on each project. |
November 20 |
|
"Interface Specification" due in class |
December 6 |
|
Final exams (during class) |
December 13 |
|
Project 2 due |
Acknowledgment: The material used in this course has been prepared and compiled
by Professor Don Chiarulli.
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