I recieved the Best Graduate Poster Presentation Award from the university of Pittsburgh.
I am a fourth-year Ph.D. student in Computer Engineering Program at University of Pittsburgh. I work in the computer science department where I am advised by Prof. Rami Melhem. Prior to joining the University of Pittsburgh, I received my B.Sc. and M.Sc. degrees both in Electrical Engineering from Shiraz University of Technology and Iran University of Science and Technology. My research interests are robust, energy efficient, and high performance computer architecture and systems.
I recieved the Best Graduate Poster Presentation Award from the university of Pittsburgh.
Our paper, Mitigating Wordline Crosstalk using Adaptive Trees of Counters has been accepted for presentation in 45th International Symposium on Computer Architecture (ISCA), Los Angeles, CA, USA.
Our paper, Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM has been accepted for presentation in 24th International Symposium on High Performance Computer Architecture (HPCA), Vienna, Austria.
Our paper, Mitigating Bitline Crosstalk Noise in DRAM Memories has been accepted for presentation in International Symposium on Memory Systems (MEMSYS), Washington, DC, USA.
I recieved the CS50 Merit Pre-doctoral Fellowship Award from the university of Pittsburgh.
Our paper, "A Variable Length Coding Framework for Cost Function Reduction in Non-Volatile Memory Systems" has been accepted for presentation in 8th Annual Non-Volatile Memories Workshop (NVMW), San Diego, CA, USA.
Our paper, "Counter-Based Tree Structure for Row Hammering Mitigation in DRAM" has been accepted for publication in IEEE Computer Architecture Letters (CAL).
Our paper, "Leveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM" has been accepted for presentation in 46th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Toulouse, France.
Our paper, "Improving Bit Flip Reduction for Biased and Random Data" has been accepted for publication in IEEE Transactions on Computers (TC).
Our paper, "PRES: Pseudo-Random Encoding Scheme to Increase the Bit Flip Reduction in the Memory" has been accepted for presentation in 52th ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, USA.
Our paper, "CAFO: Cost aware flip optimization for asymmetric memories" has been accepted for presentation in 21th IEEE International Symposium on High Performance Computer Architecture (HPCA), San Francisco, CA, USA.