homework 1

Homework 1 (due September 5, 2019)

The purpose of this homework is to make sure that you review the material covered in the computer organization course. To submit your homework you can either bring in to class a hard copy of your answer or email a soft copy (doc or pdf file) to the TA before class time.

Question 1:

Consider a MIPS program with the following mix of instructions

 
	45%	R-type arithmetic instructions
	25%	lw instructions
	15%	sw instructions
	15%	beq instructions

Assume that the instruction mix for this program is typical of all the programs that execute on a 2.5 GHz machine in which the R-type instructions execute in 5 cycles, the lw and sw instructions in 6 cycles and the beq instructions in 3 cycles. What is the the average CPI (clock per instruction) for that machine?
Assume that it is possible to increase the frequency of execution to 2.7 GHz by changing the architecture such that beq executes in 4 cycles rather than 3 cycles. Would you recommend that change? Justify your answer.
Assume that it is possible to modify the compiler such that the total number of executed instructions is increased by 5% but that the new instruction mix is changed to 50%, 20%, 15% and 15% for R-type, lw, sw and beq instructions, respectively. Would you recommend this modified compiler for any of the two machines (the 2.5 and 2.7 GHz machines).

Question 2

Following the format given in slides 15 and 16 of the first lecture, determine the formal for each instruction and the decimal values of each instruction field for the following program segment:

    
  Loop: lw      $t1, 26 ($s1)
        add     $s2, $t1, $s2
        sub    	$s1, $s1, $t2
        bne     $s1, $t3, Loop

Give also the machine code instructions (32 bits per instruction) for See Appendix A.10 of the textbook for op-codes of operands.

Question 3:

In this question, we will augment the signle cycle processor architecture which implements R-type, lw, sw and beq instructions to add a new type of instructions,

R-type-rm $r1, $r2, $r3 This instruction type is similar to the R-type instructions except that the second operand is found in the memory location whose address is found in $r3, which is different than the "R-type $r1, $r2, $r3" instructions, where the second operand is found in $r3. Note that in both the "R-type" and $R-type-rm" instructions, the first operand is found in $r2 and the result is stored in $r1. In other words the new instruction, "R-type-rm $r1, $r2, $r3", is equivalent to "lw $t1, 0 ($r3)" follwed by "R-type $r1, $r2, $t1".

Using this figure, modify the data paths to add the new instruction type. Produce a new figure, either by modifying the ppt file or just drawing the new data paths and muxes on top of print-outs of the figure. Your new figure should name any new control signals that you need to add (if any).
Specify the values of the control signals (the ones already in the figure plus the new ones that you may have to introduce) that are needed for the execution of the new instruction type. You do not have to specify the ALUop control signal since the figure uses only one ALUop signal as opposed to the two ALUop1 and ALUUop2 signals specified in Table 4.18 of the textbook.

NOTE that the order of the registers in the assembly language instruction is different from the order in the machine (binary) instruction. Specifically, in a machine instruction, $r2 and $r3 are stored in bits 25-21 and 20-16, respectively, while $r1 is stored in bits 15-11.

Question 4

In this question, we examine how latencies of individual components of the processor datapath affect the clock cycle time. For this question, assume the following latencies for logic blocks in the datapath and assume that blocks not listed have zero latencies:

I-Mem: 200ps           Add: 100ps             ALU: 180ps
Regs read: 95ps        Regs write:95ps        D-Mem: 200ps
PC read: 10ps          Mux: 10ps              Sign-extend: 5ps

Given that the delay for the lw instruction is the longest among the R-type, lw, sw and beq instructions, the delay for lw determines the cycle time. Compute the delay for the lw instruction (and hence the cycle time) for the architecture shown in this figure.
Compute the delays for the new instructions that you added in Question 3.
How will the delays for the R-type, lw, sw and beq instructions change after the modifications that you made in Question 3 to add the R-type-rm instructions?
What is the cycle time for the modified architecture of Question 3.
In your answer to each part of this question, do not just give a number as your answer -- you need to justify your answer.