assert_cycle_sequence

Ensures that if a specified necessary condition occurs, it is followed by a specified sequence of events.


	Parameters: severity_level num_cks necessary_condition property_type msg coverage_level	Class: n-cycle assertion

Syntax

Parameters


	severity_level	Severity of the failure. Default: ‘OVL_ERROR.
	num_cks	Width of the event_sequence argument. This parameter must not be less than 2. Default: 2.
	necessary_condition	Method for determining the necessary condition that initiates the sequence check and whether or not to pipeline checking. Values are: ‘OVL_TRIGGER_ON_MOST_PIPE, ‘OVL_TRIGGER_ON_FIRST_PIPE and ‘OVL_TRIGGER_ON_FIRST_NOPIPE. Default: ‘OVL_TRIGGER_ON_MOST_PIPE.
	property_type	Property type. Default: ‘OVL_ASSERT.
	msg	Error message printed when assertion fails. Default: “VIOLATION”.
	coverage_level	Coverage level. Default: ‘OVL_COVER_ALL.

Ports


	clk		Clock event for the assertion. The checker samples on the rising edge of the clock.
	reset_n		Active low synchronous reset signal indicating completed initialization.
	event_sequence [ num_cks - 1: 0 ]		Expression that is a concatenation where each bit represents an event.

Description

The assert_cycle_sequence assertion checker checks the expression event_sequence at the rising edges of clk to identify whether or not the bits in event_sequence assert sequentially on successive rising edges of clk. For example, the following series of 4-bit values (where b is any bit value) is a valid sequence:

This series corresponds to the following series of events on successive rising edges of clk:


cycle 1	event_sequence[3] == 1
cycle 2	event_sequence[2] == 1
cycle 3	event_sequence[1] == 1
cycle 4	event_sequence[0] == 1

The checker also has the ability to pipeline its analysis. Here, one or more new sequences can be initiated and recognized while a sequence is in progress. For example, the following series of 4-bit values (where b is any bit value) constitutes two overlapping valid sequences:

This series corresponds to the following sequences of events on successive rising edges of clk:


cycle 1	event_sequence[3] == 1
cycle 2	event_sequence[2] == 1
cycle 3	event_sequence[1] == 1	event_sequence[3] == 1
cycle 4	event_sequence[0] == 1	event_sequence[2] == 1
cycle 5		event_sequence[1] == 1
cycle 6		event_sequence[0] == 1

When the checker determines that a specified necessary condition has occurred, it subsequently verifies that a specified event or event sequence occurs and if not, the assertion fails.

The method used to determine what constitutes the necessary condition and the resulting trigger event or event sequence is controlled by the necessary_condition parameter. The checker has the following actions:

are sampled equal to 1 sequentially on successive rising edges of clk. When this condition occurs, the checker verifies that the value of event_sequence[0] is 1 at the next rising edge of clk. If not, the assertion fails.

The checking is pipelined, which means that if event_sequence[num_cks -1] is sampled equal to 1 while a sequence (including event_sequence[0]) is in progress and subsequently the necessary condition is satisfied, the check of event_sequence[0] is performed (unless the first sequence resulted in a fatal assertion violation).

The necessary condition is that the event_sequence [num_cks -1] bit is sampled equal to 1 on a rising edge of clk. When this condition occurs, the checker verifies that the bits:

are sampled equal to 1 sequentially on successive rising edges of clk. If not, the assertion fails.

The checking is pipelined, which means that if event_sequence[num_cks -1] is sampled equal to 1 while a check is in progress, an additional check is initiated.

The necessary condition is that the event_sequence [num_cks -1] bit is sampled equal to 1 on a rising edge of clk. When this condition occurs, the checker verifies that the bits:

are sampled equal to 1 sequentially on successive rising edges of clk. If not, the assertion fails.

The checking is not pipelined, which means that if event_sequence[num_cks -1] is sampled equal to 1 while a check is in progress, it is ignored, even if the check is verifying the last bit of the sequence (event_sequence [0]).

Assertion Check


	ASSERT_CYCLE_SEQUENCE	The necessary condition occurred, but it was not followed by the event or event sequence.
	illegal num_cks parameter	The num_cks parameter is less than 2.

Cover Point


	sequence_trigger	The trigger sequence occurred.

See also

Examples


assert_cycle_sequence #(
	‘OVL_ERROR, 3, ‘OVL_TRIGGER_ON_MOST_PIPE, ‘OVL_ASSERT, “Error: invalid WR sequence”, ‘OVL_COVER_ALL)		// severity_level // num_cks // necessary_condition // property_type // msg // coverage_level
	valid_write_sequence (
		clk, reset_n, { r_opcode == ‘WR, r_opcode == ‘WAIT, (r_opcode == ‘WR) \|\| (r_opcode == ‘DONE)} );	// clock // reset // event_sequence

Ensures that a ‘WR, ‘WAIT sequence in consecutive cycles is followed by a ‘DONE or ‘WR. The sequence checking is pipelined.


assert_cycle_sequence #(
	‘OVL_ERROR, 3, ‘OVL_TRIGGER_ON_FIRST_PIPE, ‘OVL_ASSERT, “Error: invalid WR sequence”, ‘OVL_COVER_ALL)		// severity_level // num_cks // necessary_condition // property_type // msg // coverage_level
	valid_write_sequence (
		clk, reset_n, { r_opcode == ‘WR, (r_opcode == ‘WAIT) \|\| (r_opcode == ‘WR), (r_opcode == ‘WAIT) \|\| (r_opcode == ‘DONE)} );	// clock // reset // event_sequence

Ensures that a ‘WR is followed by a ‘WAIT or another ‘WR, which is then followed by a ‘WAIT or a ‘DONE (in consecutive cycles). The sequence checking is pipelined: a new ‘WR during a sequence check initiates an additional check.


assert_cycle_sequence #(
	‘OVL_ERROR, 3, ‘OVL_TRIGGER_ON_FIRST_NOPIPE, ‘OVL_ASSERT, “Error: invalid WR sequence”, ‘OVL_COVER_ALL)		// severity_level // num_cks // necessary_condition // property_type // msg // coverage_level
	valid_write_sequence (
		clk, reset_n, { r_opcode == ‘WR, (r_opcode == ‘WAIT) \|\| (r_opcode == ‘WR), (r_opcode == ‘DONE)} );	// clock // reset // event_sequence

Ensures that a ‘WR is followed by a ‘WAIT or another ‘WR, which is then followed by a ‘DONE (in consecutive cycles). The sequence checking is not pipelined: a new ‘WR during a sequence check does not initiate an additional check.