Also, PCSource - 0 is for updating the PC to PC+4.  That is because
the value in ALUOut will be available next cycle.  right?
When you use a register value, its value had to be set during the
previous cycle.




From: Jan Wiebe <wiebe@cs.pitt.edu>
To: trh13+@pitt.edu
Cc: wiebe@cs.pitt.edu
Subject: timing in multicycle datapath
Date: Wed, 31 Oct 2007 15:54:41 -0400

Hi Toby -- remember last semester when we discussed timing of the BEQ
(ALUOp has the branch instrution, and PC is updated in cycle 3; but
ALU is used during cycle 3 to compare rs and rt)

I'm trying to come up with a description of the multicycle
datapath such that the branch instruction makes sense.    I want a
"cartoonish" treatment that makes the diagrams make sense.

I'm assuming all the registers are edge-triggered on rising edge (but
rising or falling doesn't matter)

What do you think?  Suggestions otherwise?



===Add instruction stored at address X in memory

rising edge of cycle 1
PC already contains X

During cycle 1:
   Memory[PC] is accessed  m1

   PC + 4 is calculated    m2

rising edge of cycle 2:  IR <-- m1
                         PC <-- m2

During cycle 2:
   rs and rt are accessed       m3,m4
   branch address calculated    m5

rising edge of cycle 3:  A <- m3; B <- m4; ALUOut <- m5

During cycle 3:
  A op B calculated  m6

rising edge of cycle 4:  ALUOut <- m6

During cycle 4:
  ALUOut sent to register file

rising edge of cycle 1 of next instruction:
   reg RD <-- ALUOut

==BEQ

Cycles 1 and 2 are the same.

rising edge of cycle 3:  A <- m3; B <- m4; ALUOut <- m5
  where m5 is the branch address.

During cycle 3:
   A sub B is calculated  m10
   
rising edge of cycle 1 of next instruction:

   PC <-- ALUOut, which is m5
   ALUOut <-- m10, the result of the sub

So, before this edge:

   PC:  m2

   ALUOut:  m5

   result of ALU: m10
   zero of ALU: 1 (let's say they are equal)

at the edge:

   PC:  m2
          ^
          |
   ALUOut:  m5    ^
                  |
   result of ALU: m10
   zero of ALU: still has to have its value
   
And, the control signals for a particular cycle -- e.g., PCWrite == 1
for cycle 1 -- need to hold their values through the changes made on
the rising edge of the next cycle.

I still think this looks confusing...

Thanks for any suggestions.