From VM Mon Jan 15 15:31:22 2007 X-VM-v5-Data: ([nil nil nil nil nil nil nil nil nil] ["6260" "Monday" "15" "January" "2007" "15:28:52" "-0500" "wiebe@cs.pitt.edu" "wiebe@cs.pitt.edu" nil "159" "MIPS syntax guide" "^From:" nil nil "1" nil nil nil nil nil nil nil nil] nil) Return-Path: Received: from webmail.cs.pitt.edu (lisa.cs.pitt.edu [130.49.220.147]) by maggie.cs.pitt.edu (8.13.3/8.13.3) with ESMTP id l0FKSqCL017012 for ; Mon, 15 Jan 2007 15:28:52 -0500 (envelope-from wiebe@cs.pitt.edu) Received: from 69.17.59.201 (SquirrelMail authenticated user wiebe) by webmail.cs.pitt.edu with HTTP; Mon, 15 Jan 2007 15:28:52 -0500 (EST) Message-ID: <21348.69.17.59.201.1168892932.squirrel@webmail.cs.pitt.edu> User-Agent: SquirrelMail/1.4.4 MIME-Version: 1.0 Content-Type: multipart/mixed;boundary="----=_20070115152852_17201" X-Priority: 3 (Normal) Importance: Normal X-Spam-Score: -100.812/5 BAYES_00,HTML_30_40,HTML_MESSAGE,HTML_TAG_EXIST_TBODY,NO_REAL_NAME,USER_IN_WHITELIST SA-version=3.000002 X-Scanned-By: MIMEDefang 2.51 on 130.49.220.148 From: wiebe@cs.pitt.edu To: wiebe@cs.pitt.edu Subject: MIPS syntax guide Date: Mon, 15 Jan 2007 15:28:52 -0500 (EST) ------=_20070115152852_17201 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit ------=_20070115152852_17201 Content-Type: text/html; name="cs462_mips_assembly_syntax_guide.html" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="cs462_mips_assembly_syntax_guide.html" CS 462 Mips Assembly Language Syntax Guide

CS 462 - Advanced Computer Organization, Fall 2006
Mips Assembly / Machine Language Syntax Guide

For the final part of the Verilog project, you will need to write and verify assembly code and machine code.  I find this very difficulty for Mips, so I've written this guide sheet.

It's easy to memorize or to look on the green card to see the machine language sequence of fields.  For example, an R-format's instruction fields are in this order: opcode-rd-rs-rt-shamt-funct.
Unfortunately, the assembly language syntax does not always follow this sequence.  You do not always write rs before rt.

First, memorize these mnemonics:

This first table concisely describes the proper format for each of 5 categories of instructions.  This table is useful for checking the correspondence between assembly language and machine language.

Instruction Group Assembly Language Syntax Machine Language Format Contents of registers or operand fields
Arith/Logic
 
Opcode rd, rs, rt R rs = first operand
rt = second operand
rd = result
Shift Opcode rd, rt, shamt R rt = input
shamt = # of bits places to shift
rd = result
Arith/Logic Immediate Opcode rt, rs, immediate I rs = first operand
immediate = second operand
rt = result
Mem Opcode rt, immediate(rs) I rt = data
rs = address offset
immediate = constant base address
Branch Opcode rs, rt, immediate I rs = first operand
rt = second operand
immediate = relative address

You may notice some surprises.  The Shift instructions do not use rs.  The order of rs and rt in Branch instructions are the opposite of rs and rt in Arith/Logic Immediate instructions.  There is some underlying logic to this.

First, here are the General Guidelines:

Now, here are the the Complications and Exceptions:

This second table really has the same information as the first table, but it phrases it to be more useful for seeing the correspondence between high-level language and assembly language.

Instruction Group Assembly Language Interpreted Syntax Comments
Arith/Logic
 
Opcode result, first, second result = first Op second
Shift Opcode result, input, shiftAmt result = input ShiftedBy shiftAmt
Arith/Logic Immediate Opcode result, first, second result = first Op second
Mem Opcode regData, base(offset) Load moves M[base(offset)] --> regData
Store moves regData --> M[base(offset)]
Branch Opcode first, second, relativeAddr If (first Op second), then goto relativeAddr
Example: BLT $2, $5, 13
If ($2 < $5), then skip ahead 13 instructions
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