Types of memory
Memory banks on the mini-board
Block diagram of a typical microcontroller
Components of the CPU relevant to instruction fetch/execute
Fetch/execute cycle

RAM: random access memory
can write, erase each location in same amt of time
volatile

ROM: read only memory
programmed at factory; readable only (cheap)

PROM: programmable ROM
receive it ``clean''; can program it once;
readable only

EPROM: erasable programmable ROM
erased by exposing chip to UV light for 30 minutes;
long wait between code downloads.

EEPROM: electically erasable programmable ROM
If chip contains an EEPROM progrmmer, it can
erase its own EEPROM; matter of seconds.

All ROM technologies above: non-volatile

==============================================
Memory banks on the mini-board
(Find diagram in the programmar's reference manual)
---------------------------------------------------
RAM
(random-access 00 --- FF Variables
memory) (256 bytes)

Register block 1000-103F Peripheral Device
(64 bytes) Interfaces
 

Boot ROM look in programmar's reference manual

EEPROM F800-FFFF Instructions
(Electrically-erasable  programmable read-only memory)

number of bytes of EEPROM?
FFFF-F800 + 1
7FF + 1 = 800_16
= 8 * (16^2) = 2^3 * 2^8 = 2^11 = 2048_10

End of EEPROM reserved for ``interrupt vectors''
FFC0-FFFF

======================================================
Block diagram of the typical microcontroller
--------------------------------------------

See lecture for "MCU diagram"

-- control lines into the board, e.g. reset
-- clock
-- memory banks
-- I/O data registers (peripheral device interfaces)
I/O pins are grouped into ``ports''
I/O registers contain bits for:
Control-configuration:
analog sensor -- continuous readings? 4 and stop?
Status: is the A/D conversion complete?
Data: the received or transmitted data itself
--Buses (not shown in this diagram: buses between CPU and memory)

=============================================
Components of the CPU:
User-accessible CPU registers
-------------------------------

A,B: general purpose 8-bit accumulators
D

X,Y: 16 bit index registers
used simply to hold data, or in
``indexed addressing mode'', manipulate addresses
(for accessing components of structured data types)

Condition-code register
(find, in appendix A, an example of when they are set)

PC: holds the address of the instruction to be
executed next -- 16 bits

To begin a program, what must be placed in the PC?
The address of the first instruction

As instructions are executed, the PC is incremented.

SP: stack pointer

==================================================
Components of the CPU
-----------------------
See figure "CPU diagram" in lecture

Control sequencer, or control unit
Generates signals for:
memory transfers,
ALU ops,
routing of info within the CPU,
etc.

Clock:
Keeps things working in lock-step fashion.
Each cycle, the control unit generates signals
for what should occur during that cycle

Memory transfers:
Control signals: R/~W (plus others like status)
Address bus
Memory address register
Data Bus
Memory data register
(depends on architecture)

E.g's: read (22)
---------
CPU places 22 on address bus
CPU places 1 on R/~W line
memory sends (22) back over data bus

write value 4 to location 100
-----------------------------
CPU places 100 on address bus
CPU places 4 on data bus
CPU places 0 on R/~W line

Instruction decoder, instruction register

The first byte of an instruction is the opcode
Placed in the instruction register and decoded

Line needed from instruction decoder to control unit:

the opcode determines which signals must be
generated to execute the instruction

Program counter: must be updated as the program is
executed; may have load, clear, inc function

Note: the address sent over the address bus often,
but not always, comes from the PC

When doesn't it? (note this now; will understand this below)

in indexed addressing, address is calculated,
not = (PC) (indexed addressing is our next topic)

direct and extended addressing modes like, e.g.,
LDAA Width .... Width must be sent over address bus,
and (PC) not = Width
(see *** below for an example)
=================================================
Fetch/execute cycle
--------------------
The PC contains the address of the next instruction
to be executed

Fetch the instruction:

A. Fetch opcode, which is stored in (PC), and
      increment PC
B. Fetch operands, if there are any, and update PC so it contains the address
      of the next instruction

A. Perform the operation
B. Write result back to memory, if applicable

See lecture for:  Intuitive example, related to the "Bus" and "CPU" diagrams
drawn in lecture

Description of part (h), page A-3, reference manual

Cycle by cycle execution charts tied to the "CPU" diagram
(column "Addr" shows what's on the address bus,
column "Data" shows what's on the data bus,
R/~W is the read/write control line)

=================================================
Instruction execution: Examples
---------------------------------

Understand this to get the most out of Appendix A,
and to understand assembly and execution

Assumption: PC is incremented as instruction bytes
are read from memory

Show, for each cycle:
-- Short description
-- (PC) at the beginning of the cycle
-- If there is a memory transfer:
address placed on the address bus
value transferred over the data bus
value on the R/~W line
otherwise, write ``no mem transfer''
-- Any changes to memory locations or registers
      A, B, X, or Y

If you need to refer to a value later, just
give it a name.

------------------------------------------------
Example 1:

LDAA width
Assume:
Symbol Table: width = 32
memory: (32) = 15
instruction storage: (f810) = 96; (f811) = 32
(PC) = f810

Cycle 1: fetch opcode
(PC) = f810
f810 placed on address bus
1 on the R/~W line
96 transferred on data bus

Cycle 2: fetch address of operand - dd
(PC) = f811
f811 placed on address bus
1 on the R/~W line
32 transferred over data bus

Cycle 3: read operand -- (dd)
(PC) = f812
32 placed on address bus (***)
1 on the R/~W line
15 transferred over data bus
AccA <--- 15
---------------------------------------------
EXAMPLE 2: STY Sum
Assume: (PC) = f80f, (f80f) = 18, (f810) = df, (f811) = 77,
(IX) = 43be, and ``Sum'' is a label for address 77.

Cycle 1: fetch prebyte
(PC) = f80f
f80f placed on address bus
1 on the R/~W line
18 transferred on data bus

Cycle 2: fetch opcode
(PC) = f810
f810 placed on address bus
1 on the R/~W line
df transferred on data bus

Cycle 3: fetch address -- dd
(PC) = f811
f811 placed on address bus
1 on the R/~W line
77 transferred on data bus

Cycle 4: high byte of (IY) --> 77
(PC) = f812
77 placed on address bus (***)
43 transferred on data bus
0 on the R/~W line
43 --> 77

Cycle 5: low byte of (IY) --> 78
(PC) = f812
78 placed on address bus
BE transferred on data bus
0 on the R/~W line
BE --> 78
----------------------------------------------
EXAMPLE 3: ADDD arg1
Assume: (AccD) = 0052, arg1 = 10, (10):(11) = 00AE
The instruction is stored at f803, and (PC) = f803
(the colon means concatenation)

0052_16
00AE_16
--------
0100_16

52_16 = 16*5 + 2 = 82_10
AE_16 = 10*16 + 14 = 174_10
0100_16 = 16^2 = 2^8 = 256_10

Cycle 1: fetch opcode
(PC) = f803
f803 placed on address bus
1 on the R/~W line
D3 transferred on data bus

Cycle 2: fetch address of operand -- dd
(PC) = f804
f803 placed on address bus
1 on the R/~W line
10 transferred on data bus

Cycle 3: read hi byte of operand -- (dd)
(PC) = f805
10 placed on address bus
1 on the R/~W line
00 transferred on data bus

Cycle 4: read lo byte of operand -- (dd+1)
(PC) = f805
11 placed on address bus
1 on the R/~W line
AE transferred on data bus

Cycle 5: addition performed
(PC) = f805
No mem transfer
(AccD) = 0052 is first ALU input
00AE is second ALU input
0052+00AE = 0100 --> AccD
============================================