Introduction

In this class we have seen basic bit, or boolean, operations -- AND, OR, NOT, and XOR. We said that these operations are not only useful for logical conditions (in high level programmig languages), but are also useful at the bit level -- for testing and changing individual bits. Since a bit is a 1 or a 0, and a logic value is True or False, these operations are equivalent whether you are talking about bits or logical values.

Actually, these basic operations are also the basic components that the physical circuits on a chip are built out of -- and in digital electronic terms, they are called gates. Well, actually the lowest level on a chip are transistors -- essentially electronic switches, but then these are used to build gates. So, all of the CPU operations that we can program at assembly level are basically designed into the hardware in terms of gates. And it takes alot of gates -- CPU's like the Pentium have millions of gates.

These basic boolean operations form a discrete mathematical system called boolean algebra. It obeys many of the properties that we are used to seeing in math, and more:

OR is represented by a plus sign, AND by a dot (or nothing, like multiplication). NOT is a bar over the term (but sometimes a prime mark), and XOR is most often a plus sign inside of a circle
like integer math's plus operator, 0 is the boolean identity value for OR -- that is, anything OR'd with zero is itself.
like integer math's multiply operator, 1 is the boolean identity value for AND -- that is, anything AND'd with 1 is itself.
AND and OR are associative, commutative, and distributive.

commutative: w + y = y + w; wy = yw
associative: (w + y) + z = w + (y + z); (wy)z = w(yz)
distributive: w + yz = (w + y)(w + z); w(y + z) = wy + wz

NOT defines an inverse value
DeMorgan's Laws: not(w + y) = not w not y; not(wy) = not w + not y.

Since circuit designers like to draw their circuits rather than just write formulas, there are a set of diagrams for each operator in Boolean logic: Basic Digital Gates

There is also an EX-OR gate. Its diagram is an OR gate with a curved line to the left.

Boolean Algebra

We can write down formulas in boolean math.

Their meaning can be verified by using a truth table.
There are many equivalent experssions and logic networks for any particular truth table. Two logic expressions and logic netword are equivalent if they have identical truth tables.

It is often important to perform logic minimization (simplification) to reduce the cost of implementation. To simplify logic expressions, we perform algebraic manipulations using the identities above. We'll measure cost as the count of the total number of gates and gate inputs.

To simplify: group product terms in pairs that differ only that one contains x and the other not x. Factor using the distributive rule, and you are left with x + not x, which is 1. An example will show what we mean:

f1 = not x1 not x2 not x3 + not x1 not x2 x3 + not x1 x2 x3 + x1 x2 x3. Cost is 21. (picture in lecture)

= (not x1 not x2)(not x3 + x3) + (not x1 + x1) x2 x3
= not x1 not x2 + x2 x3. Cost is 9. (picture in lecture)

Combinatorial Circuits

Output depends only on the current input

Decoders

Takes an N-bit number as input and uses it to set to 1 exactly one of the 2^n output lines.

Example application: a memory consisting of eight chips, each containing 8K bytes. Chip 0 has addresses 0 -8191, chip1 has addresses 8192-16,383, and so on. The top three bits of the address but select one of the eight memory chips. They are the three inputs to a 3-to-8 bit decoder; the outputs of the decoder are chip-enable control lines of the memory chips. (See diagram in lecture.)

Multiplexers and Demultiplexers

Multiplexer: 2 ^N inputs, one data output, and N control lines that select one of the data inputs.
An application is in gating data that may come from a number of different sources. For example, loading a 16-bit data register loaded from one of four distinct sources can be accomplicated with 16 four-input multiplexers (see diagram in lecture). As an another application, a multiplexer can be used for parallel to serial data conversion, by putting 8 bits of data on the input lines and then stepping the control lines sequentially from 000 to 111.

A demultiplexer: routes its single input to one of 2^N outputs, depending on the values of the N control lines.

Comparator

A comparator compares two input words. Where did we see this type of circuit?

The OCx timing systems.

Adders

Truth table for 1-bit addition:

A B Sum Carry
0    0    0         0
0    1    1         0
1    0    1         0
1    1    0         1

A circuit for computing both the sum and the carry is called a half adder.
The sum?

A EX-OR B.

The Carry?

An AND gate.

(Picture in lecture).

This is ok for adding the lowest order bits, but for all others, we need to handle a carry from the right.
A full adder handles carry in, carry out, and the sum. The truth table:

A B     Carry in     Sum    Carry out
0   0         0                  0             0
0   0         1                  1             0
0   1         0                  1             0
0   1         1                  0             1
1   0         0                  1             0
1   0         1                  0             1
1   1         0                  0             1
1   1         1                  1             1

A full adder is built from two half adders (picture in lecture).

sum = (A EX-OR B) EX-OR Carry in; (the number of 1s is odd)
carry out = ((A and B) or ( (A EX-OR B) and Carry in).

To build an adder for, say, two 16-bit words, just replicate the full-adder 16 times. The carry out of a bit is used as the carry into its left neighbor. The carry into the irghtmost bit is wired to 0. This type of adder is called a ripple carry adder, because any carries have to ripple all the way through before the addition is complete.

Flip Flops

We need memory circuits, which remembers the last value they were set to.

A sequential circuit is one in which the outputs depend on the input and the current state.

Well, what happens if we connect some logic gates in a special circular fashion?

(picture in lecture of an SR flip-flop).

In an SR (set reset) flip-flop, the outputs will remain set according to the last high input. If the last high input was set (S), the output will be Q high and not Q low, but if the last high input was reset (R) the output will be Q low and not Q high.

Suppose:   R=0, S=0, which they are most of the time. For argument's sake, let us assume that Q=1, not Q=0 (which means that S, not R, was last 1).
Now, suppose R becomes 1: Q becomes 0 not Q becomes1.
Then: R goes to 0 --> nothing changes!   not Q is still 1, remembering that R was high.
              S goes to 1 --> Q goes to 1, not Q goes to 0.
              S goes to 0 --> nothing changes!

So far, we've seen two stable states with R=S=0: Q=1 and not Q=0 or vice versa.

With R=S=0, consider the outputs Q=0; not Q=0.

This is inconsistent, because if an output is 0, one of the inputs must be 1.

With R=S=0, consider the outputs Q=1, not Q=1.

This is inconsistent: Consider the S nor gate, for example, S = 0, the other input (the output of the R nor gate) is 1, so it's output should be 0, not 1. The same is true for the R nor gate.

So, with R=S=0, there are only two stable states.

The state R=S=1; Q= notQ = 0 is consistent; however, it becomes nondeterministic when the inputs return to 0. (If one drops to 0 before the other, the one remaining 1 longest wins. ) But R=S=1 is not used in most applications.

Clocked SR Flip-Flop: The SR flip-flop above is asynchronous. As soon as one of the inputs changes, a short time later, the output will change. The change depens on the gate propagation delay. This is undesirable, since we are unable to determine example when the output states have reached a stable state, and it is easy for such circuits to become involved in race conditions.
That is, the sequence of events in the logic is determined by the gate delays; thus, it is impossible to ensure that the outputs of several logic sequences will occur simultaneously if they are to be used as inputs to a common gate. One way to control these timing problems is to use the system close (see diagram in class). The clock is normally 0. With the clock 0, both AND gates output 0, independent of S and R, and the latch does not change state. When the clock is 1, the effect of the and gates vanishes and the latch becomes sensitive to S and R.

Terminology:
The terms flip-flop and latch are used in different ways. Definition 1: the basic cross-coupled pair of NOR gates is a latch; the clocked version is a flip-flop. Definition 2: a flip-flop is edge triggered (the state transition does not occur when the clock is 1 but during the clock transition from 0 to 1 or from 1 to 0); a latch is level-triggered (when the clock is 1, the current values of R and S are sampled and stored in the latch; otherwise, the input has no effect. This is the version we saw above; often requires very short pulses on the clock line).

With the SR flip-flop, we just have the two control lines. We would like to have a data line. In a D flip-flop (diagram in class), S and R are derived from a single input D. At a clock pulse, the Q output is set to 1 if D = 1, or is reset to 0, if D = 0. So, the value of of the input, D, is stored in Q. Put 8 of these together and you can build the HC11 register A.