• March 15, 2018

    I recieved the Best Graduate Poster Presentation Award from the university of Pittsburgh.

  • March 13, 2018

    Our paper, Mitigating Wordline Crosstalk using Adaptive Trees of Counters has been accepted for presentation in 45th International Symposium on Computer Architecture (ISCA), Los Angeles, CA, USA.

  • Oct 20, 2017

    Our paper, Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM has been accepted for presentation in 24th International Symposium on High Performance Computer Architecture (HPCA), Vienna, Austria.

  • June 16, 2017

    Our paper, Mitigating Bitline Crosstalk Noise in DRAM Memories has been accepted for presentation in International Symposium on Memory Systems (MEMSYS), Washington, DC, USA.

  • April 20, 2017

    I recieved the CS50 Merit Pre-doctoral Fellowship Award from the university of Pittsburgh.

  • Jan 23, 2017

    Our paper, "A Variable Length Coding Framework for Cost Function Reduction in Non-Volatile Memory Systems" has been accepted for presentation in 8th Annual Non-Volatile Memories Workshop (NVMW), San Diego, CA, USA.

  • Sept 22, 2016

    Our paper, "Counter-Based Tree Structure for Row Hammering Mitigation in DRAM" has been accepted for publication in IEEE Computer Architecture Letters (CAL).

  • June 28, 2016

    Our paper, "Leveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM" has been accepted for presentation in 46th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Toulouse, France.

  • Jan 28, 2016

    Our paper, "Improving Bit Flip Reduction for Biased and Random Data" has been accepted for publication in IEEE Transactions on Computers (TC).

  • Feb 17, 2015

    Our paper, "PRES: Pseudo-Random Encoding Scheme to Increase the Bit Flip Reduction in the Memory" has been accepted for presentation in 52th ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, USA.

  • Feb 7, 2015

    Our paper, "CAFO: Cost aware flip optimization for asymmetric memories" has been accepted for presentation in 21th IEEE International Symposium on High Performance Computer Architecture (HPCA), San Francisco, CA, USA.