Power Aware Computing Systems

With Daniel Mosse

The goal of this project is to minimize power consumption in real-time computer systems within the larger context of maximizing system performance and reward while still meeting deadlines. The reward/power/deadlines objective is achieved by first developing new schemes for power-aware real-time systems, including scheduling algorithms, power control of memory resources, speed control of CPUs, and dynamic power monitoring and mode changes. The new schemes have to be integrated into the appropriate components of the system. For example, power control of memory resources requires new hardware capabilities, corresponding operating system support, and algorithms for taking advantage of these mechanisms.

CA-RAM (content addressable random access memory)

With Sangyeun Cho

Search (content lookup) is a key operation in many real-world applications including network packet processing and speech recognition. In this research, we aim to design a search-capable memory architecture that has better performance, power and cost characteristics than existing software- and hardware-only solutions. Of particular interest is the application of CA-RAM to IP packet forwarding, classification and filtering.

Phase Change Memory

With Bruce Childers and Daniel Mosse

This project intends to create an energy-efficient main memory using PCM. To achieve this goal, the proposed architecture should provide similar performance, cost and density as a DRAM-only main memory. A lifetime of at least 7 years, comparable to the useful lifetime of a server, is the smallest acceptable.

Network Security

With Daniel Mosse and Taieb Znati

This research project focuses on providing tolerance to fault and attacks in a unified way. We use resource management as a tool to achieve this goal. Intrusion detection mechanisms are assumed and two types of faults, namely, benign malfunctions and malicious intrusions, will be considered. The former can be caused by a faulty, yet legitimate client that accidentally loses control over its behavior, while the latter occurs with the intent to cause damage, such as Denial of Service (DoS). Both types of faults can severely affect the performance of the network and compromise the integrity and security of its services.

Compiler and Chip Multiprocessor Co-design for Scalable Efficient Data Access and Communication (a continuation of a previous project)

With Sangyeun Cho and Alex Jones (ECE)

A key limiting factor of performance in chip multiprocessors (CMPs) is latency of providing data to the cores. There have been several efforts to reduce this latency through architectural design optimizations such as improved cache organizations and better networks-on-chip (NoCs). However, these optimizations are limited in scope because they do not fully exploit the inherent data access locality that exists in most parallel programs. The premise of this project is that data access locality can often be discovered through compiler analysis and communicated to the architecture through the operating system where it is leveraged for improved performance and reduction in communication latency and power.

Thus, this research proposes a cooperatively designed system that includes the compiler, operating system, cache organization, and NoC. Specifically, using compiler analysis, data is classified based on its usage modes into shared, private, and mostly private access. A hybrid cache organization is proposed to use placement and location strategies that are most appropriate for each access mode. Compiler analysis is also used for determining the communication paths frequently used for data access and the configurable interconnect is programmed to establish fast and energy efficient connections on these paths.