COE1502 Architecture Instruction Set
In this course we will be creating a processor which implements a subset of the MIPS R2000 architecture. Due to limitations in space and time, we will not be attempting to implement any floating point operations, integer multiply and divide operations, and certain operations dealing with the multiply/divide hardware and coprocessors. The core operations which remain can be grouped as follows:
The above operations are those that are physically implemented in the hardware of our CPU. Most MIPS assemblers, including the one which accompanies the simulator SPIM, also accept pseudo-operations. A pseudo-operation is a single assembly language instruction which is translated by the assembler into a short sequence of actual operations. Pseudo-operations are not assigned their own opcodes. An example of a pseudo-operation would be the instruction abs rd, rs. This could be translated into the following sequence of real operations:
slt ra, rs, $0
bne ra, $0, NEG
add rd, rs, $0
j DONENEG: sub rd, $0, rsDONE:
Below can be found a listing of the MIPS R2000 Assembly Language instruction formats that we will be implementing in our COE1502 Microprocessor divided up by the type of instruction. Each listing contains the proper syntax for use in SPIM or any other MIPS assembler, followed by a short description of what the instruction does and then the encoding of the instruction into a 32-bit binary value which will be the final instruction format.
Note that although your CPU will execute 32-bit instructions, the size of the data paths and internal registers in your CPU will be 64 bits. Your CPU will interface with memory through 24-bit long addresses and 64-bit long data (8 bytes). This has a number of ramifications: 1) only the low order 24 bits of the PC are used to specify locations of instructions, 2) two instructions (64 bits) are simultaneously fetched from memory, and 3) the format of the shift instructions will have to use six bits (rather than five) to specify the shift amount.
Register Arithmetic Operations:
add rd, rs, rt :
Puts
the sum of the integers in the register rs and
the register rt into
register rd and checks for overflow.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100000 |
addu rd, rs, rt :
Puts
the sum of the integers in the register rs and
the register rt into
register rd and does not check for overflow.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100001 |
sub rd, rs, rt :
Subtracts
the integer in register rt
from the integer in register rs, putting the
result into register rd and checks for overflow.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100010 |
subu rd, rs, rt :
Subtracts
the integer in register rt
from the integer in register rs, putting the
result into register rd and does not check for overflow.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100011 |
Register Logic Operations:
and rd, rs, rt :
Puts
the logical AND of the integers from register rs
and rt into register rd.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100100 |
or rd, rs, rt :
Puts
the logical OR of the integers from register rs
and rt into register rd.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100101 |
xor rd, rs, rt :
Puts
the logical XOR of the integers from register rs
and rt into register rd.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100110 |
nor rd, rs, rt :
Puts
the logical NOR of the integers from register rs
and rt into register rd.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
100111 |
Register Shift Operations:
sll rd, rt, shamt :
Performs
logical shift of contents of register rt
left by shamt bits, putting results into
register rd. Vacated bits are filled with 0's.
|
31-26 |
25-22 |
21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
0000 |
shamt_high |
rt |
rd |
shamt |
000000 |
srl rd, rt, shamt :
Performs
logical shift of contents of register rt
right by shamt bits, putting results into
register rd. Vacated bits are filled with 0's.
|
31-26 |
25-22 |
21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
0000 |
shamt_high |
rt |
rd |
shamt |
000010 |
sra rd, rt, shamt :
Performs
aritmetic shift of contents of register rt right by shamt bits, putting results into register rd.
Vacated bits are filled with replicas of sign bit.
|
31-26 |
25-22 |
21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
0000 |
shamt_high |
rt |
rd |
shamt |
000011 |
sllv rd, rt, rs :
Performs
logical shift of contents of register rt
left by amount specified by the lowest order six bits of the value in register rs, putting results into register rd.
Vacated bits are filled with 0's.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
000100 |
srlv rd, rt, rs :
Performs
logical shift of contents of register rt
right by amount specified by the lowest order six bits of the value in register
rs, putting results into register rd.
Vacated bits are filled with 0's.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
000110 |
srav rd, rt, rs :
Performs
arithmetic shift of contents of register rt
right by amount specified by the lowest order six bits of the value in register
rs, putting results into register rd.
Vacated bits are filled with replicas of the sign bit.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
000111 |
Register Comparison Operations:
slt rd, rs, rt :
If
the signed integer in register rs is less than
the signed integer in register rt
then store the value 0x0000_0000_0000_0001 in register rd, otherwise
store the value 0x0000_0000_0000_0000 there.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
101010 |
sltu rd, rs, rt :
If
the unsigned integer in register rs is less than
the unsigned integer in register rt then store
the value 0x0000_0000_0000_0001 in register rd, otherwise store the
value 0x0000_0000_0000_0000 there.
|
31-26 |
25-21 |
20-16 |
15-11 |
10-6 |
5-0 |
|
000000 |
rs |
rt |
rd |
00000 |
101011 |
Immediate Arithmetic Operations:
addi rt, rs, imm :
Put
the sum of the integer in register rs and the
sign extended immediate value imm into the
register rt and check
for overflow.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001000 |
rs |
rt |
imm |
addiu rt, rs, imm :
Put
the sum of the integer in register rs and the
zero extended immediate value imm into the
register rt and do
not check for overflow.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001001 |
rs |
rt |
imm |
Immediate Logic Operations:
andi rt, rs, imm :
Put
the logical AND of the value in the register rs
and the zero extended immediate value imm into
register rt.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001100 |
rs |
rt |
imm |
ori rt, rs, imm :
Put
the logical OR of the value in the register rs
and the zero extended immediate value imm into
register rt.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001101 |
rs |
rt |
imm |
xori rt, rs, imm :
Put
the logical XOR of the value in the register rs
and the zero extended immediate value imm into
register rt.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001110 |
rs |
rt |
imm |
Immediate Comparison Operations:
slti rt, rs, imm :
If
the signed integer in register rs is less than
the sign extended immediate imm then store the
value 0x0000_0000_0000_0001 in register rt,
otherwise store the value 0x0000_0000_0000_0000 there.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001010 |
rs |
rt |
imm |
sltiu rt, rs, imm :
If
the unsigned integer in register rs is less
than the zero extended immediate imm then
store the value 0x0000_0000_0000_0001 in register rt, otherwise store the value 0x0000_0000_0000_0000
there.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001011 |
rs |
rt |
imm |
Load and Store Operations:
lui rt, imm :
Load
the immediate value imm into the upper 16 bits
of register rt. The lower bits of the resgister are set to 0.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
001111 |
00000 |
rt |
imm |
lb rt, Offset(rs) :
Sign
extend the byte (low-order 8 bits) at address = Offset(rs) = rs + Offset and load it into register rt.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
100000 |
rs |
rt |
Offset |
lbu rt, Offset(rs) :
Zero
extend the byte (low-order 8 bits) at address = Offset(rs) = rs + Offset and load it into register rt.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
100100 |
rs |
rt |
Offset |
lh rt, Offset(rs) :
Sign
extend the low-order 16 bits (historically called half word in 32-bit machines) at address = Offset(rs)
= rs + Offset and load it into
register rt. The 16 bits must be aligned, meaning the address must be an
even number.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
100001 |
rs |
rt |
Offset |
lhu rt, Offset(rs) :
Zero
extend the low-order 16 bits (historically called half word in 32-bit machines)
at address = Offset(rs) = rs + Offset
and load it into register rt. The 16 bits must be aligned, meaning the
address must be an even number.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
100101 |
rs |
rt |
Offset |
lw rt, Offset(rs) :
Get
word at address = Offset(rs) = rs + Offset
and load it into register rt. The word must be aligned, meaning the
address must be evenly divisible by eight (remember, a word is 64 bits).
|
31-26 |
25-21 |
20-16 |
15-0 |
|
100011 |
rs |
rt |
Offset |
sb rt, Offset(rs) :
Store
the low byte (rightmost 8 bits) from register rt
at address = Offset(rs) = rs + Offset.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
101000 |
rs |
rt |
Offset |
sh rt, Offset(rs) :
Store
the low-order 16 bits from register rt at address
= Offset(rs) = rs + Offset.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
101001 |
rs |
rt |
Offset |
sw rt, Offset(rs) :
Store
the word (64 bits) from register rt at address
= Offset(rs) = rs + Offset.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
101011 |
rs |
rt |
Offset |
Branch Operations:
beq rs, rt, label : (label is translated to a 16 bit Offset by the assembler)
If
the integer in register rs is equal to the
integer in register rt,
then increment the program counter (PC) by Offset * 4.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000100 |
rs |
rt |
Offset |
bne rs, rt, label : (label is translated to a 16 bit Offset by the assembler)
If
the integer in register rs is not equal to the
integer in register rt,
then increment the program counter (PC) by Offset * 4.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000101 |
rs |
rt |
Offset |
bltz rs, label : (label is translated to a 16 bit Offset by the assembler)
If
the integer in register rs is less than zero,
then increment the PC by Offset * 4.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000001 |
rs |
00000 |
Offset |
bgez rs, label : (label is translated to a 16 bit Offset by the assembler)
If the integer in register rs is
greater than or equal to zero, then increment the PC by Offset * 4.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000001 |
rs |
00001 |
Offset |
bltzal rs, label : (label is translated to a 16 bit Offset by the assembler)
If
the integer in register rs is less than zero,
then increment the PC by Offset * 4 and save the address of the next
instruction in register 31.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000001 |
rs |
10000 |
Offset |
bgezal rs, label : (label is translated to a 16 bit Offset by the assembler)
If
the integer in register rs is greater than or
equal to zero, then increment the PC by Offset * 4 and save the address
of the next instruction in register 31.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000001 |
rs |
10001 |
Offset |
blez rs, label : (label is translated to a 16 bit Offset by the assembler)
If the integer in register rs is
less than or equal to zero, then increment the PC by Offset * 4.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000110 |
rs |
00000 |
Offset |
bgtz rs, label : (label is translated to a 16 bit Offset by the assembler)
If the integer in register rs is
greater than zero, then increment the PC by Offset * 4.
|
31-26 |
25-21 |
20-16 |
15-0 |
|
000111 |
Rs |
00000 |
Offset |
Jump Operations:
j target :
Unconditionally
jump to instruction at L. L is
obtained by concatenating the 4 high-order bits of the PC, with the 26-bits in
the Target field and two zeros (to align the instruction address at 32-bit
boundaries).
|
31-26 |
25-0 |
|
000010 |
Target |
jal target :
Save
address of the next instruction in register 31 and then unconditionally jump to
instruction at L. L is obtained
by concatenating the 4 high-order bits of the PC, with the 26-bits in the Target
field and two zeros (to align the instruction address at 32-bit boundaries).
|
31-26 |
25-0 |
|
000011 |
Target |
jr rs :
Unconditionally
jump to instruction at address stored in rs.
|
31-26 |
25-21 |
20-5 |
4-0 |
|
000000 |
Rs |
0000000000000000 |
01000 |
jalr rs :
Save
address of the next instruction in register 31 and then unconditionally jump to
instruction at address stored in rs.
|
31-26 |
25-21 |
20-5 |
4-0 |
|
000000 |
Rs |
0000000000000000 |
01001 |
Operations Not Implemented:
mult rs, rt :
Multiply the contents of rs by rt, treating the contents as signed integers. Put the low order word of the product in lo and the high order word of the product in hi.
multu rs, rt :
Multiply the contents of rs by rt, treating the contents as unsigned integers. Put the low order word of the product in lo and the high order word of the product in hi.
div rs, rt :
Divide the contents of rs by rt, treating the contents as signed integers. Put the quotient in register lo and the remainder in register hi.
divu rs, rt :
Divide the contents of rs by rt, treating the contents as unsigned integers. Put the quotient in register lo and the remainder in register hi.
mflo rd :
Move the contents of the lo register into register rd.
mfhi rd :
Move the contents of the lo register into register rd.
mtlo rd :
Move the contents of register rs into the register lo.
mthi rd :
Move the contents of register rs into the register hi.
mfcz rt, rd :
Move the contents of coprocessor z's register rd to CPU register rt.
mtcz rt, rd :
Move the contents of CPU register rt to coprocessor z's register rd.
bczt label :
Branch to the instruction at label if coprocessor z's condition flag is true.
bczt label :
Branch to the instruction at label if coprocessor z's condition flag is false.
lwcz rt, Offset(rs) :
Load the word at address = Offset(rs) = Offset + rs into register rt of coprocessor z (0-3). The floating-point unit is z = 1.
lwl rt, Offset(rs) :
Load the left bytes from the word at the possibly unaligned address = Offset(rs) = Offset + rs into register rt.
lwr rt, Offset(rs) :
Load the right bytes from the word at the possibly unaligned address = Offset(rs) = Offset + rs into register rt.
swl rt, Offset(rs) :
Store the left bytes from register rt into the word at the possibly unaligned address = Offset(rs) = Offset + rs.
swr rt, Offset(rs) :
Store the right bytes from register rt into the word at the possibly unaligned address = Offset(rs) = Offset + rs.
All Floating Point Operations