Research Accomplishments

DRAFT Architecture

The Dynamically Reconfigurable Architectures for Factoring Tests (DRAFT) architecture was Dr. Chiarulli's Ph.D. research. Focused on one of the most computationally intensive problems of interest at the time, factoring large numbers for data encryption/decryption applications, the research resulted in the design and implementation of 256-bit computer that was reconfigurable between modes that supported single thread very long word length operations and parallel threads of shorter word length arithmetic. The design was awarded a US patent. In 1996.  This design was a predecessor to the MMX instructions that Intel incorporated into the Pentium processor and AMD's 3Dnow instruction set extensions.

[International Journal of Parallel Programming; Vol 15; No. 2; May 1987]

Coincident Pulse Addressing

This project was the first of several related projects that investigated optoelectronic bus interconnections for high-performance systems at the chip and board-level in large scale computing systems   This project focused on finding ways to perform useful logic functions, in this case address encoding and decoding, in the absence of any optical logic devices.  The problem was solved using time-of-flight encoding of signals traversing the bus over distinct optical path lengths and encoding addresses such that a pair of pulses would arrive simultaneously at the selected device.  This innovation received considerable attention in the community and was published in a feature issue of IEEE Computer that focused on Optical Computing  The idea was also awarded a US patent and is currently held in the intellectual property portfolio of the University of Pittsburgh.

[IEEE Proceedings Vol. 82, No. 11, pp. 1701-1710, Nov. 1994].

[Computer, Vol. 20, No. 12, pp. 48-57, Dec. 1987].

Partitioned Optical Passive Star (POPS)

Another significant problem with optical buses is a scalability limit imposed by the finite optical power available with each signal. The fan-out limit of each signal is bound by the available input signal power, the number of ways the input power is split across the outputs, and the signal-to-noise ratio at each receiver.  In this project, a highly scalable solution was devised that partitioned the bus into groups,  each with an optical fiber star coupler that evenly divided the optical power of a signal across all of the detectors in the group.  Each source node used multiple transmitters, one for each group. This architecture simultaneously increased the available power in the backplane and fixed the degree of fan-out, without limiting the overall size of the system.  The POPS architecture is still being studied today.  It has had resurgence in the electronic domain for architecture for managing power and wire complexity in 3D integration of multi-core processors.

 [IEEE Journal on Lightwave Technology, Vol. 14, No. 7, pp. 1601-1612, July 1996]

Optical Multi-chip Modules

For optical interconnection at the chip-scale, a great deal of research effort has been spent on developing highly parallel free space (as opposed to optical fiber) multi-chip-module (MCM) interconnection networks.  However,  a combination of physical and mechanical barriers have limited the success of free space interconnections. This project addressed these issues by substituting fiber image guides (FIGs) for free space to deliver 2D arrays of optical channels in a spatially oversampled image transported through an image guide with an array of more than 104 optical fibers per mm2. Using this system, we published the first demonstration of an FIG-imaged array of multi-channel optical interconnections connecting two chips. In subsequent research we proposed various solid polyhedron MCM structures built from rigid segments of fiber image guides with versions that incorporated optical, electrical and fluidic channels in a single substrate. These structures were also patented jointly by the University of Pittsburgh and our industry partner Schott Fiber Optics.

[Applied Optics, Vol. 39, No. 5, pp. 698-703, (10 February 2000)]

Multi-Bit-Differential Signaling

In a project that crossed over between both electronic and optical signaling domains, we devised a novel coding system that extends the benefits of differential signaling in bus applications. In differential signaling, a digital signal is sent simultaneously over two wires, one with the true signal and the other the complement. The system has several advantages for electrical signaling when compared to single ended channels. These include, constant current draw by the transmitters, fixed field modes in the transmission media, and common-mode noise rejection by the receivers. The disadvantage is the code density. It has only 50% of the capacity of an equivalent single ended channel.  In this project we made the simple observation that the advantages of differential signaling can be had in any N-choose-M signaling system for N=2M. For example,  4-choose-2 encoding over 4 wires has the same electrical transmission properties as 4 wires implemented as a pair of differential channels. However, the 4 choose 2 channel has a 50% greater code density, (6/16 versus 4/16). These code density benefits grow significantly with wider buses. In further studies we demonstrated two alternative encoders and decoders, one that embeds lightweight (and in some cases weightless) error correction, and another that supports real time dynamic channel adaptation.

[IEEE Transactions on Computers, Vol. 56, No. 3, pp. 289-304, March 2007]

3D integrated Circuits

Dr. Chiarulli's most recent research is focused on 3D Integrated Circuit technology. He has two current projects.

The first is lab-on-chip application the exploits a unique property of 3D integrated devices. Most lab-on-chip systems use the top-metal layer of a chip to form electrodes or other structures that manipulate bio-particles. This layer is always characterized by the largest feature size in the given technology, typically more than 10x larger that the smallest structures (transistor gates) that can be fabricated in the semiconductor layers.  In our device we exploit a unique feature of many 3D fabrication technologies that the top chip in the stack is positioned upside down relative to the other chips in the stack and has the substrate removed.  This places the semiconductor layers at the top of the die stack and allows the use of  gate polysilicon to fabricate electrode arrays that are larger and many times more dense than other lab-on-chip devices. This allows for significantly stronger electrical fields with lower voltage requirements and enables the device to manipulate smaller (virus-scale) particles with greater precision and sensitivity than other devices. In our first prototype we have implemented the largest and most dense (1500 electrodes, each 180nm wide,  on a 400nm pitch) individually driven electrode array built to date.

[Proceedings: The IEEE International Conference on 3D System Integration (3D IC), San Francisco, CA, September 28-30, 2009]

The second 3D-IC based project is a unique Network-on-Chip (NOC) interconnection architecture for large scale multi-core processors.  3D integrated circuit technology has significantly shortened the average wire length required to fully connect a multi-core die. In this research we are comparing the wire density and power requirements of a conventional core-switched NOC architecture to an edge-routed system using an underlying interconnection network that is similar the the POPs network described previously.

[Proceedings: 2nd International Workshop on Network on Chip Architectures (NoCArc'09), Paper No. 20, Session IV, pp. 77-82, New York, NY, December 12, 2009].