BRUCE R. CHILDERS [pic], PROFESSORDepartment of Computer Science, University of PittsburghFaculty member of the Computer Engineering ProgramE-mail: childers "at" cs.pitt.edu |
RESEARCH INTERESTS (Biography, CV, Funding)Software development tools, run-time systems, computer architecture, and power/energy management for embedded and real-time systems. OCCAM: Open Curation for Computer Architecture ModelingPCM@Pitt: Energy Management for Data CentersSustainable Computing at PittCSConsortium for Adaptive CMP Compilation and OptimizationContinuous Compilation Research GroupPower-Aware Real-Time Systems GroupCustom Counterflow Pipelines for Embedded Processors |
RECENT TALKS AND ACTIVITIES (2015/2014)01/12: We will be giving a tutorial on OCCAM at ISCA 2015 11/20: Birds of a Feather at SC'14 on Interoperable Simulation 11/18: We will be giving a tutorial on OCCAM at HPCA'15 11/18: Artifact Evaluation for CGO'15 and PPoPP'15 11/14: Talk at University of New South Wales on OCCAM 10/24: Talk at University of Utah on OCCAM 08/27: Talk on creating open exchange at DOE/NSF/DoD Workshop on SoC for HPC 08/27: Talk on mod & sim needs at DOE/NSF/DoD Workshop on SoC for HPC |
SELECTED RECENT PUBLICATIONS (Complete list)Supporting Superpages in Non-Contiguous Physical Memory IEEE International Symposium on High Performance Computer Architecture (HPCA) San Francisco Bay Area, California , February 2015 Exploiting DRAM Restore Time Variations in Deep Sub-micron Scaling Design, Automation and Test in Europe (DATE) Grenoble, France , March 2015 COMeT+: Continuous Online Memory Testing with Multi-threading Extension IEEE Transactions on Computers (TC) Volume 63, Issue 7, July 2014 Writeback-Aware Bandwidth Partitioning for Multi-core Systems with PCM International Conference on Parallel Architectures and Compilation Techniques (PACT) Edinburgh, Scotland , September 2013 Bit Mapping for Balanced PCM Programming International Symposium on Computer Architecture (ISCA) Tel Aviv, Israel , June 2013 Hardware Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory ACM Transactions on Architecture and Compiler Optimization (TACO) Volume 10, Issue 2, May 2013 Delta-compressed Caching for Overcoming the Write Bandwidth Limitation of Hybrid Main Memory ACM Transactions on Architecture and Compiler Optimization (TACO) January 2013 FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Phase Change Memory The 45th Annual IEEE/ACM International Symposum on Microarchitecture (MICRO) Vancouver, Canada , December 2012 Using Utility Prediction Models to Dynamically Choose Program Thread Counts IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) New Brunswick, New Jersey , April 2012 Improving Write Operations in MLC Phase Change Memory International Symposium on High Performance Computer Architecture (HPCA) New Orleans, Louisiana , February 2012 ACM Transactions on Architecture and Compiler Optimization (TACO), Special Issue on High-Performance and Embedded Architectures and Compilers (HiPEAC) Paris, France , January 2012 Enabling Dynamic Binary Translation in Embedded Systems with Scratchpad Memory ACM Transactions on Embedded Computing Systems (TECS) Volume 11, Issue 4, December 2012 Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems ACM Transactions on Architecture and Compiler Optimization (TACO) Accepted February, 2011, appeared July 2011 (Vol. 8, No. 2) LLS: Cooperative Integration of Wear-Leveling and Salvaging for PCM Main Memory International Conference on Dependable Systems and Networks (DSN) Hong Kong, China , June 2011 DEFCAM: A Design and Evaluation Framework for Defect-Tolerant Cache Memories ACM Transactions on Compiler and Architecture Optimization Accepted (with minor revisions), November 2010 (to appear) CloudCache: Expanding and Shrinking Private Caches 17th International Symposium on High-Performance Computer Architecture (HPCA) San Antonio, Texas , February 12-16, 2011 Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories Design Automation and Test in Europe (DATE) Grenoble, France , March 14-18, 2011 Detecting Bugs in Register Allocation ACM Transactions on Programming Languages and Systems (TOPLAS) Accepted October 2009 StimulusCache: Boosting Performance of Chip Multiprocessors with Excess Cache 16th International Symposium on High-Performance Computer Architecture (HPCA) Bangalore, India , January 9-14, 2010 PERFECTORY: A Fault-Tolerant Directory Memory Architecture IEEE Transactions on Computers (TC) Accepted May 2009, appeared May 2010, Vol. 59, No. 5, pp. 638-650 Heterogeneous Code Cache: Using Scratchpad and Main Memory in Dynamic Binary Translators 46th Design Automation Conference (DAC) San Francisco, California , July 2009 |
TEACHING |
| Updated by childers on Friday, January 23, 2015. This page renders best with FireFox. |