In 1990, Apple, IBM, and Motorola decided to implement a new RISC architecture processor that fits their new future hardware and software needs. They intended to build a high-performance, superscalar low-cost processor, since introduced as the PowerPC.
They begin with a RISC architecture, specifically the RS/6000 workstation and server, because of the large software available for such a machine. These machines were based on the POWER architecture. Their goal was to have a high-volume, single-chip microprocessor based on the POWER architecture, so that the RS/6000 machines’ existing software would continue to work given the new processor. The RISC, or Reduced Instruction Set Computer, architecture was first introduced by John Cocke in the mid 1970’s, with further refinements developed by David Paterson who coined the term “RISC”. The first machine to implement the RISC architecture was the IBM 801 machine. It clearly showed that simplifying the instruction set enables a bubble-free pipeline with average CPI of one.
IBM improved the 801 to have a superscalar, complier-targeted, reduced instruction path length, and floating point handling machine, named the POWER architecture. The POWER architecture incorporated lots of the RISC characteristics such as: fixed-length instructions, register-to-register architecture, simple addressing modes, a large general register file, and three-operand instruction format. Additionally, it has other features more characteristic of more complex ISAs. We address four of them below.
First, the architecture was designed to be superscaler, dispatched across three independent units: the branch, fixed-point arithmetic, and floating point units. This allows out of order execution.
Second, it added several compound instructions. An example of such an instruction is updating the base register on a load and store with the newly calculated effective address, thus eliminating the need for extra add instructions, otherwise required to increment the index for array traversals. Although this is a compound instruction, it does not affect the RISC pipeline flow because the updated address is already computed and a register file write port is normally available while waiting on the memory operation.
Third, it does not implement delayed branches. In a superscalar machine delayed branches are ineffective, because a single branch delay cycle induces multiple instruction bubbles that cannot all be covered with a single delay slot. Instead the POWER architecture uses a branch target buffer, and the now well known branch folding technique.
A forth factor that differentiates the POWER architecture from many other RISC type machines is its branching technique. The POWER architecture has eight condition registers that are set by compare instructions. One additional bit in the opcode of each instruction signaled that that instructions should be executed only under certain conditions, a form of predicated execution. This model is consistent with having independent execution units, and eases the compiler’s task on scheduling for setting the condition codes as well as easy handling of the branch target buffer and branch folding. This technique of predicated execution was not a feature of prior RISC architectures.
In order to maintain RS/6000 software compatibility, the PowerPC adapted the POWER architecture, and many enhancements were added. Those changes were meant to provide the following: a low-cost, single-chip, superscalar, multiprocessor capable, and 64-bit processor. Below we summarize some of the changes and enhancements from the POWER architecture.
The PowerPC architecture maintains the same basic programming model and instruction opcode assignments as the POWER architecture; it also permits both a 32 and a 64 bit address space.
The first PowerPC microprocessor was the PowerPC 601. It is a medium sized and medium performance processor. It was designed as a transitional processor from the POWER architecture to the PowerPC architecture. The 601 microprocessor includes a more sophisticated branch unit, and allows for multiple processors using Motorola’s 88110 microprocessor bus interface. It is capable of dispatching three “out-of-order” instructions per cycle.
The second PowerPC microprocessor was the 603. It has a smaller die size than the 601, with a smaller cache but approximately the same performance. It is also superscalar, dispatching three instructions per cycle. It has five concurrent execution units, and employs register renaming, reservation stations, speculative execution, and out-of-order instruction execution. It operates at 3.3 Volts (3.6 Volts for 601), and has automatic power-down circuitry.
The 604 and 620 microprocessors were developed in the sequel of the PowerPC production line. Both are aimed for higher performance. The 604 was based on the 32-bit architecture while the 620 is a 64-bit architecture.